Memory devices include a plurality of memory cells. A memory cell of a memory device, such as, for example, a memory cell of a DRAM, may include a transistor serving as a switch and a capacitor for storing electrical charges corresponding to data. A logic level of the data stored in a capacitor of a memory cell may be high (logic level 1) or low (logic level 0) depending upon the amount of the electrical charges stored in the capacitor.
Theoretically, while data is stored in the form of electrical charges in a memory cell capacitor, there is no loss of data or power consumption. However, due to a leakage current, the stored electrical charges may be degraded and the corresponding data lost. For example, a leakage current may arise from a PN junction of a metal oxide semiconductor (MOS) transistor. For preventing the degradation of the stored electrical charges and possible data loss, memory cells are typically read and recharged periodically, an operation commonly referred to as a refresh operation.
Typically, a memory controller applies a refresh command to a memory device periodically at a predetermined period which takes into account a data retention time of the memory device. For example, when the data retention time of the memory device is 64 ms, the refresh operation should be repeated for all the memory cells of the memory device at a time period which is less or equal to 64 ms.
If in a test process employed during manufacturing, the data retention time of some memory cells included in the memory device is determined not to reach the predetermined refresh period, the memory device is considered as defective and is discarded. Discarding memory devices having memory cells with insufficient retention times decreases substantially the manufacturing yield of memory devices. Also, data retention times of memory cells may be degraded due to various factors even after manufacturing, so that memory cells may cause errors even though the memory device has passed the test process. Hence, improvements are desirable.